There are many different memory devices available for use in electronic systems. The type of memory device chosen for a specific application depends largely upon what features of the memory are best suited to perform the particular function. For instance, dynamic random access memories (DRAMs) and static random access memories (SRAMs) are used to temporarily store program information and data “actively” being used by a microprocessor or other control device. To date, dynamic random access memories have been the most commonly used RAM for electronic applications. Random access memories tend to provide greater storage capability and programming options and cycles than read only memories, but they must be continually powered in order to retain their content. Most dynamic random access memories store data in the form of charged and discharged capacitors contained in an array of memory cells. Such memory cells, however, are volatile in that the stored charges will dissipate after a relatively short period of time because of the natural tendency of an electrical charge to distribute itself into a lower energy state. For this reason, most dynamic random access memories must be periodically refreshed, that is, the stored value must be rewritten to the cells, for example, every 100 milliseconds in order to retain the stored data in the memory cells. Even SRAMs, which do not require refreshing, will retain stored data only as long as power is supplied to the memory device. When the power supply to the memory device is turned off, the data is lost.
Efforts have been underway to create a commercially viable memory device that is programmable, randomly accessed, and nonvolatile. To this end, various implementations of such nonvolatile random access memory devices are presently being developed which store data in a plurality of memory cells by structurally, chemically, or magnetically changing the resistance across the memory cells in response to predetermined voltages respectively applied to the memory cells. Examples of such variable resistance memory devices include those based on polymers, perovskites, doped amorphous silicon, magnetic devices, and chalcogenide glass.
Resistance variable memory is a RAM that has electrical resistance characteristics that can be changed by external influences. The basic component of a resistance variable memory cell is a variable resistor. The variable resistor can be programmed to have high resistance or low resistance (in two-state memory circuits), or any intermediate resistance value (in multi-state memory circuits). The different resistance values of the resistance variable memory cell represent the information stored in the resistance variable memory circuit. The advantages of resistance variable memory are the simplicity of the circuit, leading to smaller devices, the non-volatile characteristic of the memory cell, and the stability of the memory states. The resistance variable memories that are being researched and developed include but not limited to Magnetic RAM (MRAM), Oxide RAM and Phase Change RAM (PCRAM). Among these different resistance variable memory technologies, PCRAM is one of the most promising candidates for next generation memory technology due to its various advantages such as high density, high speed, better scalability, low cost and low power.
Phase change memory technology utilizes a thermally induced reversible structural phase change between amorphous and polycrystalline states of the cell material. The rapid and reversible phase change gives rise to a change of cell material resistance, which can be measured electrically by the read operation. The amorphous state has a higher resistivity, while the polycrystalline state has a lower resistivity. Both phase states are nonvolatile and can retain their states at room temperature or elevated temperatures (up to 85 C) up to 10 years. The phase change is accomplished by Joule heating the cell material with a set or rest programming current pulse. To switch the cell material or a portion of cell material from low-resistivity polycrystalline state to high-resistivity amorphous state, a short but large RESET pulse is applied to heat up the cell above the material meting point. Subsequently the molten cell material is rapidly cooled down by thermal conduction through surrounding material and is quenched into a solid state that retains the disorder inherent in the molten state, which is termed amorphous state without long range order. The cooling rate has to be larger than 1011 K/s for the quenching to be effective. To switch the cell from amorphous state back to the low-resistivity stable polycrystalline state, a longer but lower SET pulse is applied to raise the cell material temperature to above its crystallization temperature but below its melting temperature. The SET pulse has to be sufficiently longer than the material crystallization time to ensure the crystallization process is complete.
Since the cell needs to be heated up above the melting temperature within a very short time to reset the memory, it is necessary to supply a sufficiently large RESET current to the memory cell. The requirement of large RESET current is one of the biggest issues with phase change memory, which can be of the order of 1 mA for the state-of-the-art phase change memory technology. Because of the large RESET current requirement, large access transistors and large cell size are implemented in the current phase change memory design. The cell size is larger than 16 f2 if a CMOS MOSFET is used as the access transistor, while it is slightly smaller at 10 f2 if a bipolar transistor is used as the access transistor, where f is the minimum line width of the process node, even though the cell size can be smaller if a cross point diode-accessed configuration is utilized for the cell circuit design. The large cell size impedes low cost large scale phase change memory integration to compete with other existing non-volatile memory such as NOR or NAND flash. On the other hand, phase change memory can be easily scaled down to smaller feature size, with functionality demonstrated even down to 5 nm. The operational mechanism and underlying physical principles dictates the scaling rule of phase change memory, in which the RESET current can scale inversely to the bottom electrode contact area. In order to reduce the transistor and cell size and increase the memory data density, the development of the phase change memory technology in the past has mostly focused on the reduction of the programming current requirement by reducing the contact area between the bottom electrode and the phase change cell. The present invention addresses the desire to reduce the programming current requirement for a phase change cell by restructuring the contact area between the cell and bottom electrode by means of a novel process technique to achieve an effective ultra-small contact area that is inaccessible with the current photolithography or spacer technologies.
The present invention describes various bottom electrode contact structures for a semiconductor device and in particular a phase change memory semiconductor device and methods to form same, that reduces set and reset current requirements by reducing the effective contact area between the cell and bottom electrodes of the phase change cell.